/* * EPWM_int.c * * Created on: 2018锟斤拷10锟斤拷9锟斤拷 * Author: Administrator */ ＃i nclude "EPWM_int.h" #define ISR_FREQUENCY 20 #define SYSTEM_FREQUENCY 150 //#define DSP28335_EPWM_OSHT1
float32 T = 0.001/ISR_FREQUENCY;
Uint16 PWM_PeriodMax=0, PWM_HalfPerMax=0 ,PWM_Deadband=0 ;
void EPWM6_int(void) { PWM_PeriodMax=SYSTEM_FREQUENCY*1000000*T/2; PWM_HalfPerMax=PWM_PeriodMax/2; PWM_Deadband =4.0*SYSTEM_FREQUENCY;//4us EALLOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;//TB_DIV2; // Clock ratio to SYSCLKOUT TBCLK=SYSCLKOUT/(2鐨凨娆?2HSPCLKDIV) EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; EPwm2Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; EPwm3Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; EPwm4Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; EPwm5Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN; EPwm6Regs.TBCTL.bit.CTRMODE=TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBPRD = PWM_PeriodMax; EPwm2Regs.TBPRD = PWM_PeriodMax; EPwm3Regs.TBPRD = PWM_PeriodMax; EPwm4Regs.TBPRD = PWM_PeriodMax; EPwm5Regs.TBPRD = PWM_PeriodMax; EPwm6Regs.TBPRD = PWM_PeriodMax;
EPwm1Regs.TBPHS.half.TBPHS = 0; EPwm2Regs.TBPHS.half.TBPHS = 2; EPwm3Regs.TBPHS.half.TBPHS = 2; EPwm4Regs.TBPHS.half.TBPHS = 2; EPwm5Regs.TBPHS.half.TBPHS = 2; EPwm6Regs.TBPHS.half.TBPHS = 2;
// EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.FREE_SOFT =2; EPwm2Regs.TBCTL.bit.FREE_SOFT =2; EPwm3Regs.TBCTL.bit.FREE_SOFT =2; EPwm4Regs.TBCTL.bit.FREE_SOFT =2; EPwm5Regs.TBCTL.bit.FREE_SOFT =2; EPwm6Regs.TBCTL.bit.FREE_SOFT =2;
EPwm1Regs.TBCTL.bit.PHSDIR = 1; EPwm2Regs.TBCTL.bit.PHSDIR = 1; EPwm3Regs.TBCTL.bit.PHSDIR = 1; EPwm4Regs.TBCTL.bit.PHSDIR = 1; EPwm5Regs.TBCTL.bit.PHSDIR = 1; EPwm6Regs.TBCTL.bit.PHSDIR = 1;
EPwm1Regs.TBCTL.bit.PRDLD = 1;/////////////////0 EPwm2Regs.TBCTL.bit.PRDLD = 1; EPwm3Regs.TBCTL.bit.PRDLD = 1; EPwm4Regs.TBCTL.bit.PRDLD = 1; EPwm5Regs.TBCTL.bit.PRDLD = 1; EPwm6Regs.TBCTL.bit.PRDLD = 1;
EPwm1Regs.CMPCTL.all = 0;//锟斤拷锟斤拷影锟接寄达拷锟斤拷+0时1//1:Active compare A EPwm2Regs.CMPCTL.all = 0; EPwm3Regs.CMPCTL.all = 0; EPwm4Regs.CMPCTL.all = 0; EPwm5Regs.CMPCTL.all = 0; EPwm6Regs.CMPCTL.all = 0; /*SVPWM模式 EPwm1Regs.AQCTLA.all = 0x0060; // 0x0090;CAD_SET + CAU_CLEAR 0x0060;CAU_SET+CAD_CLEAR EPwm2Regs.AQCTLA.all = 0x0060; EPwm3Regs.AQCTLA.all = 0x0060; EPwm4Regs.AQCTLA.all = 0x0060; EPwm5Regs.AQCTLA.all = 0x0060; EPwm6Regs.AQCTLA.all = 0x0060; */ /*PWM模式*/ EPwm1Regs.AQCTLA.all = 0x0090; // 0x0090;CAD_SET + CAU_CLEAR 0x0060;CAU_SET+CAD_CLEAR EPwm1Regs.AQCTLA.bit.ZRO=0x02; EPwm2Regs.AQCTLA.all = 0x0090; EPwm3Regs.AQCTLA.all = 0x0090; EPwm3Regs.AQCTLA.bit.ZRO=0x02; EPwm4Regs.AQCTLA.all = 0x0090; EPwm5Regs.AQCTLA.all = 0x0090; EPwm5Regs.AQCTLA.bit.ZRO=0x02; EPwm6Regs.AQCTLA.all = 0x0090;
// EPwm1Regs.DBCTL.all = 0x0003+0x0008; // EPWMA双锟斤拷锟斤拷锟斤拷 EPWMB锟斤拷转 使锟斤拷双锟斤拷锟斤拷时 EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//锟铰斤拷锟斤拷锟斤拷时 EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.CMPA.half.CMPA=0; EPwm2Regs.CMPA.half.CMPA=0; EPwm3Regs.CMPA.half.CMPA=0; EPwm4Regs.CMPA.half.CMPA=0; EPwm5Regs.CMPA.half.CMPA=0; EPwm6Regs.CMPA.half.CMPA=0;
EPwm1Regs.DBFED = PWM_Deadband; EPwm1Regs.DBRED = PWM_Deadband; EPwm2Regs.DBFED = PWM_Deadband; EPwm2Regs.DBRED = PWM_Deadband; EPwm3Regs.DBFED = PWM_Deadband; EPwm3Regs.DBRED = PWM_Deadband; EPwm4Regs.DBFED = PWM_Deadband; EPwm4Regs.DBRED = PWM_Deadband; EPwm5Regs.DBFED = PWM_Deadband; EPwm5Regs.DBRED = PWM_Deadband; EPwm6Regs.DBFED = PWM_Deadband; EPwm6Regs.DBRED = PWM_Deadband;
EPwm1Regs.PCCTL.all = 0; EPwm2Regs.PCCTL.all = 0; EPwm3Regs.PCCTL.all = 0; EPwm4Regs.PCCTL.all = 0; EPwm5Regs.PCCTL.all = 0; EPwm6Regs.PCCTL.all = 0;
EPwm1Regs.TZSEL.all = 0; EPwm2Regs.TZSEL.all = 0; EPwm3Regs.TZSEL.all = 0; EPwm4Regs.TZSEL.all = 0; EPwm5Regs.TZSEL.all = 0; EPwm6Regs.TZSEL.all = 0;
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; EPwm1Regs.ETSEL.bit.INTEN = 1; EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; //锟斤拷锟斤拷1锟斤拷 锟叫讹拷 2ND
EDIS; /* Disable EALLOW*/ }
void HVDMC_Protection(void) {
EALLOW;
#ifdef DSP28335_EPWM_OSHT1 EPwm1Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT EPwm2Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT EPwm3Regs.TZSEL.bit.OSHT1 = 1; //enable TZ1 for OSHT #else EPwm1Regs.TZSEL.bit.CBC1=0x1; EPwm2Regs.TZSEL.bit.CBC1=0x1; EPwm3Regs.TZSEL.bit.CBC1=0x1; EPwm4Regs.TZSEL.bit.CBC1=0x1; EPwm5Regs.TZSEL.bit.CBC1=0x1; EPwm6Regs.TZSEL.bit.CBC1=0x1; // EPwm1Regs.TZSEL.bit.CBC1=0x0;//ee关闭TZ // EPwm2Regs.TZSEL.bit.CBC1=0x0; // EPwm3Regs.TZSEL.bit.CBC1=0x0; // EPwm4Regs.TZSEL.bit.CBC1=0x0; // EPwm5Regs.TZSEL.bit.CBC1=0x0; // EPwm6Regs.TZSEL.bit.CBC1=0x0; // EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm5Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EDIS; #endif #ifdef DSP28335_EPWM_OSHT1 EPwm1Regs.TZCLR.bit.OST = 1; EPwm2Regs.TZCLR.bit.OST = 1; EPwm3Regs.TZCLR.bit.OST = 1; #endif }
void closeBridge(void) { EALLOW;
EPwm1Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm2Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm3Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm4Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm5Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm6Regs.DBCTL.bit.OUT_MODE=DB_DISABLE;
EPwm1Regs.AQCSFRC.bit.CSFA=1; EPwm1Regs.AQCSFRC.bit.CSFB=1; EPwm2Regs.AQCSFRC.bit.CSFA=1; EPwm2Regs.AQCSFRC.bit.CSFB=1; EPwm3Regs.AQCSFRC.bit.CSFA=1; EPwm3Regs.AQCSFRC.bit.CSFB=1; EPwm4Regs.AQCSFRC.bit.CSFA=1; EPwm4Regs.AQCSFRC.bit.CSFB=1; EPwm5Regs.AQCSFRC.bit.CSFA=1; EPwm5Regs.AQCSFRC.bit.CSFB=1; EPwm6Regs.AQCSFRC.bit.CSFA=1; EPwm6Regs.AQCSFRC.bit.CSFB=1;
EDIS; }
void closeBridgeStep(void) { EALLOW;
EPwm1Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm2Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm3Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm4Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm5Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm6Regs.DBCTL.bit.OUT_MODE=DB_DISABLE;
EPwm1Regs.AQCSFRC.bit.CSFA=1; EPwm1Regs.AQCSFRC.bit.CSFB=0; EPwm2Regs.AQCSFRC.bit.CSFA=0; EPwm2Regs.AQCSFRC.bit.CSFB=1; EPwm3Regs.AQCSFRC.bit.CSFA=1; EPwm3Regs.AQCSFRC.bit.CSFB=0; EPwm4Regs.AQCSFRC.bit.CSFA=0; EPwm4Regs.AQCSFRC.bit.CSFB=1; EPwm5Regs.AQCSFRC.bit.CSFA=1; EPwm5Regs.AQCSFRC.bit.CSFB=0; EPwm6Regs.AQCSFRC.bit.CSFA=0; EPwm6Regs.AQCSFRC.bit.CSFB=1;
EDIS; } void setBridgeHigh(void) { EALLOW;
EPwm1Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm2Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm3Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm4Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm5Regs.DBCTL.bit.OUT_MODE=DB_DISABLE; EPwm6Regs.DBCTL.bit.OUT_MODE=DB_DISABLE;
EPwm1Regs.AQCSFRC.bit.CSFA=2; EPwm1Regs.AQCSFRC.bit.CSFB=2; EPwm2Regs.AQCSFRC.bit.CSFA=2; EPwm2Regs.AQCSFRC.bit.CSFB=2; EPwm3Regs.AQCSFRC.bit.CSFA=2; EPwm3Regs.AQCSFRC.bit.CSFB=2; EPwm4Regs.AQCSFRC.bit.CSFA=2; EPwm4Regs.AQCSFRC.bit.CSFB=2; EPwm5Regs.AQCSFRC.bit.CSFA=2; EPwm5Regs.AQCSFRC.bit.CSFB=2; EPwm6Regs.AQCSFRC.bit.CSFA=2; EPwm6Regs.AQCSFRC.bit.CSFB=2;
EDIS; } //################################################# //CSFA CSFB 锟侥达拷锟斤拷锟斤拷锟斤拷0锟斤拷 强锟斤拷锟斤拷锟绞? //----------------------------------------------- void setPWMFree(void) { EALLOW;
EPwm1Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE; EPwm2Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE; EPwm3Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE; EPwm4Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE; EPwm5Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE; EPwm6Regs.DBCTL.bit.OUT_MODE=DB_FULL_ENABLE;
EPwm1Regs.AQCSFRC.bit.CSFA=0; EPwm1Regs.AQCSFRC.bit.CSFB=0; EPwm2Regs.AQCSFRC.bit.CSFA=0; EPwm2Regs.AQCSFRC.bit.CSFB=0; EPwm3Regs.AQCSFRC.bit.CSFA=0; EPwm3Regs.AQCSFRC.bit.CSFB=0; EPwm4Regs.AQCSFRC.bit.CSFA=0; EPwm4Regs.AQCSFRC.bit.CSFB=0; EPwm5Regs.AQCSFRC.bit.CSFA=0; EPwm5Regs.AQCSFRC.bit.CSFB=0; EPwm6Regs.AQCSFRC.bit.CSFA=0; EPwm6Regs.AQCSFRC.bit.CSFB=0;
EDIS; } void openLowBridge(void) { EALLOW;
EPwm1Regs.AQCSFRC.bit.CSFA=1; EPwm1Regs.AQCSFRC.bit.CSFB=2; EPwm2Regs.AQCSFRC.bit.CSFA=1; EPwm2Regs.AQCSFRC.bit.CSFB=2; EPwm3Regs.AQCSFRC.bit.CSFA=1; EPwm3Regs.AQCSFRC.bit.CSFB=2; EPwm4Regs.AQCSFRC.bit.CSFA=1; EPwm4Regs.AQCSFRC.bit.CSFB=2; EPwm5Regs.AQCSFRC.bit.CSFA=1; EPwm5Regs.AQCSFRC.bit.CSFB=2; EPwm6Regs.AQCSFRC.bit.CSFA=1; EPwm6Regs.AQCSFRC.bit.CSFB=2;
EDIS; }
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