/*
* ADC_int.c
*
* Created on: 2018??10??9??
* Author: Administrator
*/
＃i nclude "ADC_int.h"
#define CPU_CLOCK_SPEED 15.000L // 10.000L for a 100MHz CPU clock speed
#define ADC_usDELAY 50000L
Uint16 ChSel[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
Uint16 TrigSel[16] = {5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5};
Uint16 ACQPS[16] = {8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8};
void ADC_MACRO_INIT( Uint16 *ChSel_X, Uint16 *Trigsel_X, Uint16 *ACQPS_X)
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
// AdcRegs.ADCREFSEL.bit.REF_SEL=1;
ADC_cal();
EDIS;
AdcRegs.ADCTRL3.all = 0x00E0; /* Power up bandgap/reference/ADC circuits*/
DELAY_US(ADC_usDELAY); /* Delay before converting ADC channels*/
AdcRegs.ADCTRL1.bit.ACQ_PS = ACQPS_X[0];
AdcRegs.ADCTRL1.bit.CPS = 0;
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0;
// AdcRegs.ADCTRL3.bit.SMODE_SEL= 1; //???????????
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; /* 0x0 Dual Sequencer Mode, 0x1 Cascaded Mode*/
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x0;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
AdcRegs.ADCTRL2.bit.RST_SEQ2 = 0x1;
// AdcRegs.ADCTRL1.bit.CONT_RUN=1;
// AdcRegs.ADCTRL1.bit.SEQ_OVRD=0;
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1=0x1; /* enable SOC from EPWMA trigger*/
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = ChSel_X[0];
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = ChSel_X[1];
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = ChSel_X[2];
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = ChSel_X[3];
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = ChSel_X[4];
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = ChSel_X[5];
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = ChSel_X[6];
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = ChSel_X[7];
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = ChSel_X[8];
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = ChSel_X[9];
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = ChSel_X[10];
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = ChSel_X[11];
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = ChSel_X[12];
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = ChSel_X[13];
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = ChSel_X[14];
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = ChSel_X[15];
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 13;
EDIS;
/* Set up Event Trigger with CNT_zero enable for Time-base of EPWM1 */
EPwm1Regs.ETSEL.bit.SOCAEN = 1; /* Enable SOCA */
EPwm1Regs.ETSEL.bit.SOCASEL = 2; /* Enable period event for SOCA */
EPwm1Regs.ETPS.bit.SOCAPRD = 1; /* Generate SOCA on the 1st event */
EPwm1Regs.ETCLR.bit.SOCA = 1; /* Clear SOCA flag */
}
void ADC_SOC_int(void )
{
ChSel[0]=14; // iEa
ChSel[1]=1; // ChSelect: ADC A1-> Phase A Voltage
ChSel[2]=2; // ChSelect: ADC A2-> Phase B Voltage
ChSel[3]=3; // ChSelect: ADC A3-> Phase C Voltage
ChSel[4]=4; // ChSelect: ADC A4->Phase A Current(APF)
ChSel[5]=5; // ChSelect: ADC A5-> Phase B Current(APF)
ChSel[6]=6; // ChSelect: ADC A6-> Phase C Current(APF)
ChSel[7]=9; // ChSelect: ADC B1-> Phase A Current(LOAD)
ChSel[8]=10; // ChSelect: ADC B2-> Phase B Current(LOAD)
ChSel[9]=11; // ChSelect: ADC B3-> Phase C Current(LOAD)
ChSel[10]=7; // ChSelect: ADC A7-> DC(+) Bus Voltage
ChSel[11]=15; // ChSelect: ADC B7-> DC(-) Bus Voltage
ChSel[12]=8; // ChSelect: ADC B0-> DC Bus Voltage
ChSel[13]=0; // ChSelect: ADC B7-> TEMP
ChSel[14]=12; // iEc
ChSel[15]=13; // IEb
/* ChSel[0]=0;
ChSel[1]=0;
ChSel[2]=1;
ChSel[3]=2;
ChSel[4]=3;
ChSel[5]=4;
ChSel[6]=5;
ChSel[7]=6;*/
ADC_MACRO_INIT(ChSel,TrigSel,ACQPS) ;
}
