/* * GPIO_int.c * * Created on: 2018??10??8?? * Author: Administrator */
＃i nclude "GPIO_int.h" void Init_6Gpio(void) { EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; GpioCtrlRegs.GPADIR.bit.GPIO5 = 1; GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; GpioCtrlRegs.GPADIR.bit.GPIO10= 1; GpioCtrlRegs.GPADIR.bit.GPIO11= 1;
GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; GpioDataRegs.GPACLEAR.bit.GPIO11 = 1;
EDIS; } void Init_6PWMGpio(void) { EALLOW; GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Enable pull-up on GPIO0 (EPWM1A) GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; /// Enable pull-up on GPIO0 (EPWM1A) // GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;/// GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO12 =1; // 0=GPIO, 1=TZ1, 2=SCITX-A, 3=SPISIMO-B GpioCtrlRegs.GPADIR.bit.GPIO12 = 0; //ee 1=OUTput, 0=INput DB9
EDIS; }
void Init_WATCHDOGGpio(void) { EALLOW; GpioCtrlRegs.GPADIR.bit.GPIO12 = 1; GpioDataRegs.GPASET.bit.GPIO12 = 1;
EDIS; }
void Init_RELAYGpio(void) { EALLOW; /* GpioCtrlRegs.GPADIR.bit.GPIO20 = 1; GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; GpioCtrlRegs.GPADIR.bit.GPIO23 = 1; GpioCtrlRegs.GPADIR.bit.GPIO26 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO20 = 1; GpioDataRegs.GPACLEAR.bit.GPIO21 = 1; GpioDataRegs.GPACLEAR.bit.GPIO23 = 1; GpioDataRegs.GPACLEAR.bit.GPIO26 = 1;*/ GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1; //RELAT_3 GpioDataRegs.GPBSET.bit.GPIO50 = 1; // // GpioDataRegs.GPBSET.bit.GPIO50 = 1;//???????? GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1; //RELAT_2 GpioDataRegs.GPBSET.bit.GPIO51 = 1; // GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1; //RELAT_1 GpioDataRegs.GPBSET.bit.GPIO52 = 1; // // GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1;//???????? // GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1;//???????? // GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1;//???????? EDIS;
} void Init_FAN_FAULTGpio(void) { EALLOW; GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO49 = 0; // GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0; // GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; EDIS; }
void Init_DER_FAULTGpio(void) { EALLOW; // GpioCtrlRegs.GPBDIR.bit.GPIO52 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO53 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0; EDIS; }
void Init_LOCKGpio(void) { EALLOW; GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1; //??????Ч EDIS; } //void Init_Sci485aGpio(void) //{ // EALLOW; // // GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) // GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation // // GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO29 (SCIRXDA) // GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO29 (SCIRXDA) // GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO29 for SCIRXDA operation // // GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; //485?л?λ // GpioDataRegs.GPASET.bit.GPIO22 = 1; // EDIS; //}
void Init_CAPGpio(void) { EALLOW; GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1) GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1) GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1 EDIS; }
void Init_I2CGpio() { EALLOW; GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA) GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA) GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA) GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA) GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation EDIS; } | 
